1. Field of the Invention
The present invention relates to a direct-current (DC) offset cancel circuit which is used in a demodulation circuit in a receiver in a radio communication system, such as a portable telephone, and cancels a DC component to be superimposed on a digital signal when a baseband analog signal output from a high-frequency reception section of the receiver is converted to a digital signal to be input to a demodulating section.
2. Description of the Related Art
The high-frequency reception section of the radio communication system, such as a portable telephone, converts a signal intermittently received for battery saving to a baseband analog signal, and outputs the baseband analog signal. The baseband analog signal is converted in an analog/digital (A/D) converter to a digital signal, which is in turn input to the demodulating section. The demodulating section performs error correction and takes bit synchronization and frame synchronization to execute a demodulating process.
In such a radio communication system, while the antenna input signal intermittently received undergoes frequency selection and amplification and frequency conversion in the high-frequency reception section to become a baseband analog signal, a DC component may be superimposed on the signal by analog elements or the like. If the baseband analog signal with the DC component superimposed thereon is converted to a digital signal as it is and the digital signal is then subjected to a demodulating process, the demodulating section may make a determination error depending on the threshold that is used to detect various kinds of signals. In this respect, a DC offset cancel circuit, which cancels a DC component at the circuit portion that converts the baseband analog signal to a digital signal, is used.
FIG. 5 is a block diagram showing a conventional DC offset cancel circuit 500. The DC offset cancel circuit 500 includes an A/D converter 51 which converts a baseband analog signal output from a high-frequency reception section to a digital signal, an averaging circuit 52 which acquires an average value of digital signals sequentially output from the A/D converter 51, an adder 53 which adds the digital signal output from the A/D converter to a predetermined offset value to cancel out a DC component, a determination section 55 which outputs the digital signal output from the adder 53 to a demodulating section, determines whether the digital signal is originated from a significant signal or noise, and outputs the result as significant signal/noise determination information, a control section 56 which activates the averaging circuit 52 in a zone for which the input signal is judged to be noise from the significant signal/noise determination information output from the determination section 55, writes acquired offset values on a memory 54 to be described later one by one, and stops the averaging circuit 52 in a zone for which the input signal is decided to be a significant signal and outputs the offset value stored in the memory 54 to the adder 53, and the memory 54 which writes the offset values acquired by the averaging circuit 52 one after another in response to an instruction from the control section 56.
The DC offset cancel circuit 500 is designed in such a way that the A/D converter 51 converts the baseband analog signal output from the high-frequency reception section to a digital signal to be one input of the adder 53, the averaging circuit 52 acquires the average value of the DC component of the digital signal, the control section 56 stores the average value of the DC component in the noise zone in the memory 54 according to information of the noise zone and the significant zone in the intermittent reception, acquired by the determination section 55, and the stored value is input to the other end of the adder 53 for subtraction in the significant zone (see, for example, Japanese Patent Laid-Open Publication No. H9-274539 (FIG. 2)).
FIG. 6 is a block diagram showing another conventional DC offset cancel circuit 600. The DC offset cancel circuit 600 includes a buffer 61 which receives a baseband analog signal output from a high-frequency reception section, an amplifier 52 which amplifies the output signal of the buffer 61, an A/D converter 63 which converts an analog signal output from the amplifier 62 to a digital signal, a level detector 64 which detects the output amplitude level of the A/D converter 53, an adder 65 which adds the digital signal output from the A/D converter 63 and a predetermined offset value to cancel a DC offset, a determination section 66 which outputs the digital signal output from the adder 65 to a demodulating section, determines whether the digital signal is a significant signal or noise and outputs significant signal/noise determination information, an averaging circuit 67 which computes an average value of the digital signal output from the A/D converter 63, a control section 68 which activates the averaging circuit 67 when the input signal is judged to be noise and outputs the acquired value as an offset value to a memory 69 to be described later, and stops the averaging circuit 67 when the input signal is judged to be a significant signal and outputs the offset value stored in the memory 69 to the adder 65, the memory 69 which stores the offset values acquired by the averaging circuit 67 in response to an instruction from the control section 68, a reference value register 70 in which a reference voltage value for the input signal is set and stored as a digital value beforehand, an adder 71 which adds the offset value read from the memory 69 in response to an instruction from the control section 68 to the value registered in the reference value register 70 and outputs a resultant value, and a D/A converter 72 which converts a digital value output from the adder 71 to an analog value and outputs the analog value to the buffer 61 as a DC-component removed reference voltage value.
In the DC offset cancel circuit 600, the baseband analog signal output from the high-frequency reception section is input to one input terminal of the buffer 61, is amplified by the amplifier 62, and is converted in the A/D converter 63 to a digital signal to be an input of one input terminal of the adder 65. The level detector 64 monitors the level of the digital value, and the averaging circuit 67 acquires the average value of the digital value. The control section 68 stores the average value of the DC component of noise in the memory 69 according to information on the noise or significant zone acquired by the determination section 66 and information from the level detector 64. In the significant zone, when the detected level is low, the stored value in the memory 69 is input to the subtraction terminal of the adder 65 to cancel out the DC offset, and when the detected level is high, the stored value in the memory 69 is given to the adder 71 to be added to the reference value, and the resultant value is converted in the D/A converter 72 to an analog value to be input to the other end of the buffer 61, thereby correcting a DC fluctuating component (see, for example, Japanese Patent Laid-Open Publication No. H9-331257 (FIG. 3)).